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* New upstream version 0.9Ruben Undheim2019-10-18
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Fixed trailing whitespacesClifford Wolf2015-07-02
* namespace YosysClifford Wolf2014-09-27
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Fixed a bug in "add -global_input"Clifford Wolf2013-11-21
* Added "add" command (only wires for now)Clifford Wolf2013-11-20