Commit message (Expand) | Author | Age | |
---|---|---|---|
* | namespace Yosys | Clifford Wolf | 2014-09-27 |
* | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
* | Added copy command | Clifford Wolf | 2014-02-06 |