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splice.cc
Commit message (
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Author
Age
*
Fixed memory corruption in "splice" command
Clifford Wolf
2014-12-29
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Added various new options to splice command
Clifford Wolf
2014-02-08
*
Now also move net labes to the right position in splice cmd
Clifford Wolf
2014-02-08
*
Added splice command
Clifford Wolf
2014-02-07