yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	sort cell types in "stat" output by name	Clifford Wolf	2014-10-03
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Alphabetically sort port names in "show" output	Clifford Wolf	2014-09-19
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Added "stat -width"	Clifford Wolf	2014-08-22
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22
*	Added "plugin" command	Clifford Wolf	2014-08-22
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Added mux support to wreduce command	Clifford Wolf	2014-08-05
*	Added "show -signed"	Clifford Wolf	2014-08-04
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added "trace" command	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added write_file command	Clifford Wolf	2014-07-30
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25