index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
passes
/
cmds
Commit message (
Expand
)
Author
Age
*
Fixed build with gcc-4.6
Clifford Wolf
2014-08-07
*
Various fixes and improvements in wreduce pass
Clifford Wolf
2014-08-05
*
Removed old "constmap" from wreduce code
Clifford Wolf
2014-08-05
*
Added support for truncating of wires to wreduce pass
Clifford Wolf
2014-08-05
*
Cleanups and improvements in wreduce pass
Clifford Wolf
2014-08-05
*
Added mux support to wreduce command
Clifford Wolf
2014-08-05
*
Added "show -signed"
Clifford Wolf
2014-08-04
*
Added RTLIL::IdString::in(...)
Clifford Wolf
2014-08-04
*
Progress in "wreduce" pass
Clifford Wolf
2014-08-03
*
Added "wreduce" command (work in progress)
Clifford Wolf
2014-08-03
*
Fixes in show command (related to new IdString)
Clifford Wolf
2014-08-03
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
*
Added ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf
2014-08-01
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added "trace" command
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Added write_file command
Clifford Wolf
2014-07-30
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
*
Disabled cover() for non-linux builds
Clifford Wolf
2014-07-25
*
Improvements in "cover" command
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Added "cover" command
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Added "select -assert-count"
Clifford Wolf
2014-07-20
*
Improved seeding of color rng in show command
Clifford Wolf
2014-07-18
*
Added %D and %c select commands
Clifford Wolf
2014-06-14
*
added tee cmd
Clifford Wolf
2014-06-03
*
fixed syntax error in dot file created by "show" command
Clifford Wolf
2014-05-10
*
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...
Siesh1oo
2014-03-12
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
[next]