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* Various win32 / vs build fixesClifford Wolf2014-10-17
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* Various MXE build fixesClifford Wolf2014-10-17
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* Header changes so it will compile on VSWilliam Speirs2014-10-17
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* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-15
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* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-12
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* Renamed "log.cc" to "logcmd.cc" so there aren't two "log.cc" in the source treeClifford Wolf2014-10-11
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* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-11
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* Disabled "cover -d" on win32Clifford Wolf2014-10-11
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* Moved patmatch() to yosys.ccClifford Wolf2014-10-10
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* Replaced fnmatch() with patmatch()Clifford Wolf2014-10-10
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* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* sort cell types in "stat" output by nameClifford Wolf2014-10-03
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* namespace YosysClifford Wolf2014-09-27
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* Alphabetically sort port names in "show" outputClifford Wolf2014-09-19
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* Removed $bu0 cell typeClifford Wolf2014-09-04
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* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
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* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
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* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
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* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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* Added "stat -width"Clifford Wolf2014-08-22
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
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* Added "plugin" commandClifford Wolf2014-08-22
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* Added module->uniquify()Clifford Wolf2014-08-16
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* RIP $safe_pmuxClifford Wolf2014-08-14
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* Fixed build with gcc-4.6Clifford Wolf2014-08-07
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* Various fixes and improvements in wreduce passClifford Wolf2014-08-05
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* Removed old "constmap" from wreduce codeClifford Wolf2014-08-05
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* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
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* Cleanups and improvements in wreduce passClifford Wolf2014-08-05
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* Added mux support to wreduce commandClifford Wolf2014-08-05
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* Added "show -signed"Clifford Wolf2014-08-04
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* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
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* Progress in "wreduce" passClifford Wolf2014-08-03
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* Added "wreduce" command (work in progress)Clifford Wolf2014-08-03
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* Fixes in show command (related to new IdString)Clifford Wolf2014-08-03
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
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* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added "trace" commandClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Added write_file commandClifford Wolf2014-07-30
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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