yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Imported GIT HEAD: 0.8+20190328git32bd0f2	Ruben Undheim	2019-03-28
*	New upstream version 0.7+20180830git0b7a184	Ruben Undheim	2018-08-30
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Do not detect fsm state registers with init attribute	Clifford Wolf	2015-09-21
*	Added $logic_not handling to fsm_detect	Clifford Wolf	2015-09-18
*	Bugfix in fsm_detect for complex muxtrees	Clifford Wolf	2015-08-18
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	namespace Yosys	Clifford Wolf	2014-09-27
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06
*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30
*	fixed typos	Johann Glaser	2013-03-18
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01
*	initial import	Clifford Wolf	2013-01-05