path: root/passes/fsm/
Commit message (Expand)AuthorAge
* Added log_warning() APIClifford Wolf2014-11-09
* namespace YosysClifford Wolf2014-09-27
* RIP $safe_pmuxClifford Wolf2014-08-14
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-06
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
* fixed typosJohann Glaser2013-03-18
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05