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path: root/passes/fsm/fsm_detect.cc
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* Added log_warning() APIClifford Wolf2014-11-09
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* namespace YosysClifford Wolf2014-09-27
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* RIP $safe_pmuxClifford Wolf2014-08-14
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-06
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* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
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* fixed typosJohann Glaser2013-03-18
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* Added help messages for fsm_* passesClifford Wolf2013-03-01
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* initial importClifford Wolf2013-01-05