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path: root/passes/fsm/fsm_expand.cc
Commit message (Expand)AuthorAge
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
* namespace YosysClifford Wolf2014-09-27
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Some fixes to improve determinismClifford Wolf2013-08-09
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-25
* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-24
* fixed typosJohann Glaser2013-03-18
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05