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path: root/passes/fsm/fsm_extract.cc
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
* RIP $safe_pmuxClifford Wolf2014-08-14
* Another fsm_extract bugfixClifford Wolf2014-08-08
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commandsClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-06
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Some fixes to improve determinismClifford Wolf2013-08-09
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-08
* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-05
* Added [[CITE]] tags to abc and fsm_extract passesClifford Wolf2013-03-15
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* Copy attributes from state signal to fsm cellClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05