yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands	Clifford Wolf	2014-07-22
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08
*	Renamed opt_rmunused to opt_clean	Clifford Wolf	2013-06-05
*	Added [[CITE]] tags to abc and fsm_extract passes	Clifford Wolf	2013-03-15
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01
*	Copy attributes from state signal to fsm cell	Clifford Wolf	2013-01-05
*	initial import	Clifford Wolf	2013-01-05