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* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added onehot attributeClifford Wolf2015-02-04
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Added module->uniquify()Clifford Wolf2014-08-16
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-24
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05