Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
* | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 |
* | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Replaced RTLIL::Const::str with generic decoder method | Clifford Wolf | 2013-12-04 |
* | Improved FSM one-hot encoding, added binary encoding | Clifford Wolf | 2013-05-24 |
* | Added help messages for fsm_* passes | Clifford Wolf | 2013-03-01 |
* | initial import | Clifford Wolf | 2013-01-05 |