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path: root/passes/fsm/fsm_map.cc
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* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-24
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05