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* Added module->uniquify()Clifford Wolf2014-08-16
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Another fsm_extract bugfixClifford Wolf2014-08-08
* Fixed "fsm -export"Clifford Wolf2014-08-08
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added log_cmd_error_expectionClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commandsClifford Wolf2014-07-22
* fixed memory leak in fsm_optClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Fixes in fsm detect/extract for better detection of non-fsm circuitsClifford Wolf2013-12-06
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
* Some fixes to improve determinismClifford Wolf2013-08-09
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-08
* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-05
* Added -nodetect option to fsm passClifford Wolf2013-05-24
* Improved FSM one-hot encoding, added binary encodingClifford Wolf2013-05-24
* fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-05
* fsm_export: specify KISS filename on command lineJohann Glaser2013-04-05
* Improved method for finding fsm_expand candidatesClifford Wolf2013-03-25
* Changed fsm_expand to merge multiplexers more aggressivelyClifford Wolf2013-03-24
* fixed typosJohann Glaser2013-03-18
* Added [[CITE]] tags to abc and fsm_extract passesClifford Wolf2013-03-15
* Added help messages for fsm_* passesClifford Wolf2013-03-01
* "fsm_export" pass: fix KISS file generation.Martin Schmölzer2013-02-23