yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
\|
*	Added log_warning() API	Clifford Wolf	2014-11-09
\|
*	Changed from "and" to "&&"	William Speirs	2014-10-15
\|
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
\|
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
\|
*	namespace Yosys	Clifford Wolf	2014-09-27
\|
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
\|
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
\|
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
\|
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30
\|
*	Added module->uniquify()	Clifford Wolf	2014-08-16
\|
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
\|
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
\|
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14
\|
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10
\|
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09
\|
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08
\|
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08
\|
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08
\|
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
\|
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
\|
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
\|
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
\|
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
\|
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27
\|
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
\|
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
\|
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
\|
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
\|
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
\|
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
\|
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
\|
*	SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands	Clifford Wolf	2014-07-22
\|
*	fixed memory leak in fsm_opt	Clifford Wolf	2014-07-22
\|
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
\|
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06
\|
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
\|
*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30
\|
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09
\|
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08
\|
*	Renamed opt_rmunused to opt_clean	Clifford Wolf	2013-06-05
\|