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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
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* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-24
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* Do not detect fsm state registers with init attributeClifford Wolf2015-09-21
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* Added $logic_not handling to fsm_detectClifford Wolf2015-09-18
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* Bugfix in fsm_detect for complex muxtreesClifford Wolf2015-08-18
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
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* Bugfix in fsm_extractClifford Wolf2015-07-03
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* Fixed trailing whitespacesClifford Wolf2015-07-02
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* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-29
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* Added onehot attributeClifford Wolf2015-02-04
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* Added "fsm -encfile"Clifford Wolf2015-01-30
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
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* Added log_warning() APIClifford Wolf2014-11-09
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* Changed from "and" to "&&"William Speirs2014-10-15
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* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
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* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
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* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
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* Added module->uniquify()Clifford Wolf2014-08-16
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
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* RIP $safe_pmuxClifford Wolf2014-08-14
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* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
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* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
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* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
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* Another fsm_extract bugfixClifford Wolf2014-08-08
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* Fixed "fsm -export"Clifford Wolf2014-08-08
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* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Added log_cmd_error_expectionClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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