yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	New upstream version 0.9	Ruben Undheim	2019-10-18
*	Imported GIT HEAD: 0.8+20190328git32bd0f2	Ruben Undheim	2019-03-28
*	New upstream version 0.7+20180830git0b7a184	Ruben Undheim	2018-08-30
*	Imported yosys 0.7	Ruben Undheim	2016-11-03
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Keep modules with $assume (like $assert)	Clifford Wolf	2015-07-25
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04
*	documentation improvements	Clifford Wolf	2015-03-29
*	Added hierarchy -auto-top	Clifford Wolf	2015-03-18
*	Fixed bug in "hierarchy" for parametric designs	Clifford Wolf	2015-03-04
*	Cosmetic fixes in "hierarchy" for blackbox modules	Clifford Wolf	2015-02-15
*	Fixed pattern matching in "hierarchy -generate"	Clifford Wolf	2015-01-04
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Fixed off-by-one bug in "hierarchy -check" for positional module args	Clifford Wolf	2014-12-24
*	Checking existence of ports in "hierarchy -check"	Clifford Wolf	2014-12-19
*	Fixed bug in "hierarchy -top" with array of instances	Clifford Wolf	2014-11-27
*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17
*	Header changes so it will compile on VS	William Speirs	2014-10-17
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
*	Moved patmatch() to yosys.cc	Clifford Wolf	2014-10-10
*	Replaced fnmatch() with patmatch()	Clifford Wolf	2014-10-10
*	set "keep" on modules with $assert cells in "hierarchy"	Clifford Wolf	2014-09-30
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Added module->ports	Clifford Wolf	2014-08-14
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	fixed cell array handling of positional arguments	Clifford Wolf	2014-06-07
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
*	Added hierarchy -purge_lib option	Clifford Wolf	2014-02-04
*	Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))	Martin Schmölzer	2014-01-14
*	Added hierarchy -libdir option	Clifford Wolf	2014-01-14
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24