yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08