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hierarchy
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*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Added "submod -copy"
Clifford Wolf
2016-01-08
*
Added "singleton" pass
Clifford Wolf
2015-11-07
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Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Keep modules with $assume (like $assert)
Clifford Wolf
2015-07-25
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
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documentation improvements
Clifford Wolf
2015-03-29
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Added hierarchy -auto-top
Clifford Wolf
2015-03-18
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Fixed bug in "hierarchy" for parametric designs
Clifford Wolf
2015-03-04
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Cosmetic fixes in "hierarchy" for blackbox modules
Clifford Wolf
2015-02-15
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Fixed pattern matching in "hierarchy -generate"
Clifford Wolf
2015-01-04
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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Fixed off-by-one bug in "hierarchy -check" for positional module args
Clifford Wolf
2014-12-24
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Checking existence of ports in "hierarchy -check"
Clifford Wolf
2014-12-19
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Fixed bug in "hierarchy -top" with array of instances
Clifford Wolf
2014-11-27
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Added log_warning() API
Clifford Wolf
2014-11-09
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Various win32 / vs build fixes
Clifford Wolf
2014-10-17
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Header changes so it will compile on VS
William Speirs
2014-10-17
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Do not the 'z' modifier in format string (another win32 fix)
Clifford Wolf
2014-10-11
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Moved patmatch() to yosys.cc
Clifford Wolf
2014-10-10
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Replaced fnmatch() with patmatch()
Clifford Wolf
2014-10-10
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set "keep" on modules with $assert cells in "hierarchy"
Clifford Wolf
2014-09-30
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namespace Yosys
Clifford Wolf
2014-09-27
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Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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Added module->ports
Clifford Wolf
2014-08-14
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More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
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Allow "hierarchy -generate" for $__ cells
Clifford Wolf
2014-07-29
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Added call_on_selection() and call_on_module() API
Clifford Wolf
2014-07-20
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fixed cell array handling of positional arguments
Clifford Wolf
2014-06-07
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Add support for cell arrays
Clifford Wolf
2014-06-07
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Implemented read_verilog -defer
Clifford Wolf
2014-02-13
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