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* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
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* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
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* Add support for cell arraysClifford Wolf2014-06-07
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* Implemented read_verilog -deferClifford Wolf2014-02-13
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* Moved some passes to other source directoriesClifford Wolf2014-02-08
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* Added hierarchy -purge_lib optionClifford Wolf2014-02-04
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* Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-14
| | | | | | This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* Added hierarchy -libdir optionClifford Wolf2014-01-14
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* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
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* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
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* Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-03
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* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
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* Improved log messages generated by hierarchy passClifford Wolf2013-05-26
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* Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-26
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* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
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* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-26
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* Added hierarchy -generate command for generating skeletton modulesClifford Wolf2013-03-25
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* Implemented general handler for selection argumentsClifford Wolf2013-03-03
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* Added online help for "show" and "hierarchy" commandsClifford Wolf2013-02-28
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* initial importClifford Wolf2013-01-05