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path: root/passes/hierarchy
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Added module->portsClifford Wolf2014-08-14
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
* Add support for cell arraysClifford Wolf2014-06-07
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Moved some passes to other source directoriesClifford Wolf2014-02-08
* Added hierarchy -purge_lib optionClifford Wolf2014-02-04
* Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))Martin Schmölzer2014-01-14
* Added hierarchy -libdir optionClifford Wolf2014-01-14
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04
* Remove auto_wire framework (smarter than the verilog standard)Clifford Wolf2013-11-24
* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-24
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
* Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-03
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Improved log messages generated by hierarchy passClifford Wolf2013-05-26
* Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-26
* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-28
* Collect parameters in hierarchy -generate (and do nothing with them)Clifford Wolf2013-03-26
* Added hierarchy -generate command for generating skeletton modulesClifford Wolf2013-03-25
* Implemented general handler for selection argumentsClifford Wolf2013-03-03
* Added online help for "show" and "hierarchy" commandsClifford Wolf2013-02-28
* initial importClifford Wolf2013-01-05