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path: root/passes/hierarchy
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* Added "submod -copy"Clifford Wolf2016-01-08
* Added "singleton" passClifford Wolf2015-11-07
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
* Keep modules with $assume (like $assert)Clifford Wolf2015-07-25
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* documentation improvementsClifford Wolf2015-03-29
* Added hierarchy -auto-topClifford Wolf2015-03-18
* Fixed bug in "hierarchy" for parametric designsClifford Wolf2015-03-04
* Cosmetic fixes in "hierarchy" for blackbox modulesClifford Wolf2015-02-15
* Fixed pattern matching in "hierarchy -generate"Clifford Wolf2015-01-04
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Fixed off-by-one bug in "hierarchy -check" for positional module argsClifford Wolf2014-12-24
* Checking existence of ports in "hierarchy -check"Clifford Wolf2014-12-19
* Fixed bug in "hierarchy -top" with array of instancesClifford Wolf2014-11-27
* Added log_warning() APIClifford Wolf2014-11-09
* Various win32 / vs build fixesClifford Wolf2014-10-17
* Header changes so it will compile on VSWilliam Speirs2014-10-17
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
* Moved patmatch() to yosys.ccClifford Wolf2014-10-10
* Replaced fnmatch() with patmatch()Clifford Wolf2014-10-10
* set "keep" on modules with $assert cells in "hierarchy"Clifford Wolf2014-09-30
* namespace YosysClifford Wolf2014-09-27
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Added module->portsClifford Wolf2014-08-14
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
* Add support for cell arraysClifford Wolf2014-06-07
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Moved some passes to other source directoriesClifford Wolf2014-02-08