yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16
*	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01
*	initial import	Clifford Wolf	2013-01-05