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path: root/passes/memory/memory_dff.cc
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed log messages in memory_dffClifford Wolf2014-06-01
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-01
* Added help messages to memory_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05