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* Using new obj iterator API in a few placesClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Fixed log messages in memory_dffClifford Wolf2014-06-01
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-01
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* Added help messages to memory_* passesClifford Wolf2013-03-01
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* initial importClifford Wolf2013-01-05