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memory
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memory_map.cc
Commit message (
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Author
Age
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Improved write address decoder generation memory_map
Clifford Wolf
2014-08-30
*
Using worker class in memory_map
Clifford Wolf
2014-08-30
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Changes to "memory" pass for new $memwr/$mem WR_EN interface
Clifford Wolf
2014-07-16
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Only generate write-enable $and if WE is not constant 1 in memory_map
Clifford Wolf
2014-02-02
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Fixed bug in synthesis of memories that are never written
Clifford Wolf
2013-10-17
*
Added help messages to memory_* passes
Clifford Wolf
2013-03-01
*
initial import
Clifford Wolf
2013-01-05