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path: root/passes/memory/memory_map.cc
Commit message (Expand)AuthorAge
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-16
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Only generate write-enable $and if WE is not constant 1 in memory_mapClifford Wolf2014-02-02
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
* Added help messages to memory_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05