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path: root/passes/memory/memory_share.cc
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Improved memory_share log messagesClifford Wolf2014-07-19
* More verbose memory_share help messageClifford Wolf2014-07-19
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-18
* Added memory_shareClifford Wolf2014-07-18