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passes
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memory
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memory_share.cc
Commit message (
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Author
Age
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
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Improved memory_share log messages
Clifford Wolf
2014-07-19
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More verbose memory_share help message
Clifford Wolf
2014-07-19
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Added SAT-based write-port sharing to memory_share
Clifford Wolf
2014-07-19
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Fixed bug in memory_share feedback-to-en code
Clifford Wolf
2014-07-19
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Added translation from read-feedback to en-signals in memory_share
Clifford Wolf
2014-07-18
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Only create collision detect logic in memory_share if necessary
Clifford Wolf
2014-07-18
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Added memory_share
Clifford Wolf
2014-07-18