yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04
*	Added memory_bram "shuffle_enable" feature	Clifford Wolf	2015-01-04
*	Removed left over debug code from memory_bram	Clifford Wolf	2015-01-04
*	Added "memory -bram"	Clifford Wolf	2015-01-03
*	Added memory_bram 'or_next_if_better' feature	Clifford Wolf	2015-01-03
*	memory_bram transp support	Clifford Wolf	2015-01-03
*	Progress in memory_bram	Clifford Wolf	2015-01-03
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02
*	Progress in memory_bram	Clifford Wolf	2015-01-02
*	Progress in memory_bram	Clifford Wolf	2015-01-02
*	Progress in memory_bram	Clifford Wolf	2015-01-01
*	Progress in memory_bram	Clifford Wolf	2015-01-01
*	Progress in memory_bram	Clifford Wolf	2014-12-31
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31
*	More dict/pool related changes	Clifford Wolf	2014-12-27
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30
*	Using worker class in memory_map	Clifford Wolf	2014-08-30
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21