yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
\|
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
\|
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
\|
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
\|
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
\|
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
\|
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
\|
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21
\|
*	Improved memory_share log messages	Clifford Wolf	2014-07-19
\|
*	More verbose memory_share help message	Clifford Wolf	2014-07-19
\|
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19
\|
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19
\|
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18
\|
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18
\|
*	Added memory_share	Clifford Wolf	2014-07-18
\|
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16
\|
*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01
\|
*	Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect	Clifford Wolf	2014-02-08
\|
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
\|
*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02
\|
*	Added automatic memid generation to memory_unpack command	Clifford Wolf	2014-01-17
\|
*	Added memory_unpack command	Clifford Wolf	2014-01-17
\|
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
\|
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
\|
*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01
\|
*	Fixed help message typo (memory pass)	Clifford Wolf	2013-10-30
\|
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17
\|
*	Added -nomap option to memory pass	Clifford Wolf	2013-03-21
\|
*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01
\|
*	initial import	Clifford Wolf	2013-01-05