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Commit message (Collapse)AuthorAge
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-18
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* memory_bram hotfix for memories with width 1Clifford Wolf2015-01-06
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* removed old debug codeClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-05
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* Towards Xilinx bram supportClifford Wolf2015-01-04
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* Added memory_bram "shuffle_enable" featureClifford Wolf2015-01-04
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* Removed left over debug code from memory_bramClifford Wolf2015-01-04
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* Added "memory -bram"Clifford Wolf2015-01-03
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* Added memory_bram 'or_next_if_better' featureClifford Wolf2015-01-03
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* memory_bram transp supportClifford Wolf2015-01-03
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* Progress in memory_bramClifford Wolf2015-01-03
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* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
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* Progress in memory_bramClifford Wolf2015-01-02
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* Progress in memory_bramClifford Wolf2015-01-02
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* Progress in memory_bramClifford Wolf2015-01-01
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* Progress in memory_bramClifford Wolf2015-01-01
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* Progress in memory_bramClifford Wolf2014-12-31
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* Added memory_bram (not functional yet)Clifford Wolf2014-12-31
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* More dict/pool related changesClifford Wolf2014-12-27
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-16
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
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* Using worker class in memory_mapClifford Wolf2014-08-30
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* Various improvements in memory_dff passClifford Wolf2014-08-06
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
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* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Using new obj iterator API in a few placesClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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