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* Various improvements in memory_dff passClifford Wolf2014-08-06
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Improved memory_share log messagesClifford Wolf2014-07-19
* More verbose memory_share help messageClifford Wolf2014-07-19
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-19
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-19
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-18
* Added memory_shareClifford Wolf2014-07-18
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-16
* Fixed log messages in memory_dffClifford Wolf2014-06-01
* Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-08
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* Only generate write-enable $and if WE is not constant 1 in memory_mapClifford Wolf2014-02-02
* Added automatic memid generation to memory_unpack commandClifford Wolf2014-01-17
* Added memory_unpack commandClifford Wolf2014-01-17
* Added correct handling of $memwr priorityClifford Wolf2014-01-03
* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-01
* Fixed help message typo (memory pass)Clifford Wolf2013-10-30
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
* Added -nomap option to memory passClifford Wolf2013-03-21
* Added help messages to memory_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05