yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24
*	Cleanups in opt_clean	Clifford Wolf	2014-12-29
*	dict/pool changes in opt_clean	Clifford Wolf	2014-12-29
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28
*	More hashtable finetuning	Clifford Wolf	2014-12-27
*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Fixed various VS warnings	Clifford Wolf	2014-10-18
*	Some cleanups in opt_clean	Clifford Wolf	2014-10-16
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
*	remove buffers in opt_clean	Clifford Wolf	2014-10-03
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16
*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08
*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07
*	Added $assert cell	Clifford Wolf	2014-01-19
*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08
*	Added support for "keep" attributes on wires	Clifford Wolf	2013-11-05
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17
*	Added iopadmap pass	Clifford Wolf	2013-10-16
*	Added "clean -purge" and ";;;" support	Clifford Wolf	2013-08-11
*	Added ";;" as shortcut for "; clean;"	Clifford Wolf	2013-08-11