yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added dict/pool.sort()	Clifford Wolf	2015-01-24
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*	Cleanups in opt_clean	Clifford Wolf	2014-12-29
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*	dict/pool changes in opt_clean	Clifford Wolf	2014-12-29
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*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28
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*	More hashtable finetuning	Clifford Wolf	2014-12-27
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*	Replaced std::unordered_set (nodict) with Yosys::pool	Clifford Wolf	2014-12-26
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*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
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*	Fixed various VS warnings	Clifford Wolf	2014-10-18
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*	Some cleanups in opt_clean	Clifford Wolf	2014-10-16
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
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*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
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*	remove buffers in opt_clean	Clifford Wolf	2014-10-03
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*	Added support for "keep" on modules	Clifford Wolf	2014-09-29
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*	namespace Yosys	Clifford Wolf	2014-09-27
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*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Added design->scratchpad	Clifford Wolf	2014-08-30
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16
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*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08
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*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08
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*	Added support for "keep" attributes on wires	Clifford Wolf	2013-11-05
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
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*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17
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*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17
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*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17
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*	Added iopadmap pass	Clifford Wolf	2013-10-16
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*	Added "clean -purge" and ";;;" support	Clifford Wolf	2013-08-11
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*	Added ";;" as shortcut for "; clean;"	Clifford Wolf	2013-08-11
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