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path: root/passes/opt/opt_clean.cc
Commit message (Expand)AuthorAge
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* remove buffers in opt_cleanClifford Wolf2014-10-03
* Added support for "keep" on modulesClifford Wolf2014-09-29
* namespace YosysClifford Wolf2014-09-27
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Added design->scratchpadClifford Wolf2014-08-30
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-08
* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-07
* Added $assert cellClifford Wolf2014-01-19
* Fixed keep attribute on wires in opt_cleanClifford Wolf2013-11-08
* Added support for "keep" attributes on wiresClifford Wolf2013-11-05
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-17
* Avoid re-arranging signals on register outputsClifford Wolf2013-10-17
* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-17
* Added iopadmap passClifford Wolf2013-10-16
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-11
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-11
* Some fixes to improve determinismClifford Wolf2013-08-09
* Added "clean" command (less verbose opt_clean)Clifford Wolf2013-08-08
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-07
* Added opt_clean -purge optionClifford Wolf2013-07-07
* Renamed opt_rmunused to opt_cleanClifford Wolf2013-06-05