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* Squashed commit of the following:Ruben Undheim2016-09-23
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* Added wreduce $mul support and fixed signed $mul opt_const bugClifford Wolf2015-09-25
* Added detection of "mux inverter" chains in opt_constClifford Wolf2015-09-18
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added opt_const -clkinvClifford Wolf2015-07-01
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-29
* Using design->selected_modules() in opt_*Clifford Wolf2015-02-03
* Bugfix in opt_const $eq -> buffer codeClifford Wolf2015-01-31
* Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)Clifford Wolf2015-01-13
* disabled problematic mux -> and/or transformClifford Wolf2015-01-07
* dict<> ref vs insert bugfixClifford Wolf2015-01-06
* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-28
* More hashtable finetuningClifford Wolf2014-12-27
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Improved TopoSort determinismClifford Wolf2014-11-07
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-31
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added design->scratchpadClifford Wolf2014-08-30
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added cover() calls to opt_constClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "opt_const -keepdc"Clifford Wolf2014-07-21