yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Bugfix in opt_const $eq -> buffer code	Clifford Wolf	2015-01-31
*	Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)	Clifford Wolf	2015-01-13
*	disabled problematic mux -> and/or transform	Clifford Wolf	2015-01-07
*	dict<> ref vs insert bugfix	Clifford Wolf	2015-01-06
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28
*	More hashtable finetuning	Clifford Wolf	2014-12-27
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
*	Improved TopoSort determinism	Clifford Wolf	2014-11-07
*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added "opt_const -keepdc"	Clifford Wolf	2014-07-21
*	Added mul to mux conversion to "opt_const -fine"	Clifford Wolf	2014-07-21
*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21
*	Added opt_const support for simple identities	Clifford Wolf	2014-07-21
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22
*	Fixed opt_const handling of double invert with non-1 output width	Clifford Wolf	2014-02-15
*	Added opt_const -undriven	Clifford Wolf	2014-02-06
*	More opt_const -mux_bool features	Clifford Wolf	2014-02-02