summaryrefslogtreecommitdiff
path: root/passes/opt/opt_const.cc
Commit message (Expand)AuthorAge
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added design->scratchpadClifford Wolf2014-08-30
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added cover() calls to opt_constClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "opt_const -keepdc"Clifford Wolf2014-07-21
* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-21
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
* Added opt_const support for simple identitiesClifford Wolf2014-07-21
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
* Added opt_const -undrivenClifford Wolf2014-02-06
* More opt_const -mux_bool featuresClifford Wolf2014-02-02
* Added opt_const -mux_boolClifford Wolf2014-02-02
* Added support for inverter chains to opt_constClifford Wolf2014-02-02
* Added "opt_const -mux_undef"Clifford Wolf2014-01-14
* Improved $_MUX_ handling in opt_constClifford Wolf2013-12-28
* More conservastive $eq/$ne/$eqx/$nex opt_const codeClifford Wolf2013-12-28
* More $eq/$ne/$eqx/$nex fixes in opt_constClifford Wolf2013-12-27
* Fixed/improved opt_const $eq/$ne/$eqx/$nex handlingClifford Wolf2013-12-27
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Renamed extend_un0() to extend_u0() and use it in genrtlilClifford Wolf2013-11-07
* Fixed type of sign extension in opt_const $eq/$ne handlingClifford Wolf2013-11-07
* Fixed $eq/$ne bitwise optimization in opt_constClifford Wolf2013-11-07