yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21
*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18
*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17
*	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16
*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
*	initial import	Clifford Wolf	2013-01-05