path: root/passes/opt/
Commit message (Expand)AuthorAge
* namespace YosysClifford Wolf2014-09-27
* Added design->scratchpadClifford Wolf2014-08-30
* RIP $safe_pmuxClifford Wolf2014-08-14
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-18
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-17
* improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-16
* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-12
* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Added help messages for opt_* passesClifford Wolf2013-03-01
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
* initial importClifford Wolf2013-01-05