path: root/passes/opt/
Commit message (Expand)AuthorAge
* Don't be too smart with $dff cells with "init" attribute on out signalClifford Wolf2014-10-16
* namespace YosysClifford Wolf2014-09-27
* Added design->scratchpadClifford Wolf2014-08-30
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed detection of init attribute in opt_rmdffClifford Wolf2014-02-04
* Improved handling of reg init in opt_share and opt_rmdffClifford Wolf2014-02-04
* Added constant-clock case to opt_rmdffClifford Wolf2014-02-02
* Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-17
* Added log_abort() apiClifford Wolf2013-05-24
* Some improvements in opt_rmdffClifford Wolf2013-05-23
* Added help messages for opt_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05