yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01
\| \| \| \|	RTLIL::SigChunk::data
*	Added design->scratchpad	Clifford Wolf	2014-08-30
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*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
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*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
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*	Added "opt -fast"	Clifford Wolf	2014-08-16
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
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*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Added "opt_const -keepdc"	Clifford Wolf	2014-07-21
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*	Added mul to mux conversion to "opt_const -fine"	Clifford Wolf	2014-07-21
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*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21
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*	Added opt_const support for simple identities	Clifford Wolf	2014-07-21
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*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18
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*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17
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