yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
...
*	Added "opt -fast"	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24
*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added "opt_const -keepdc"	Clifford Wolf	2014-07-21
*	Added mul to mux conversion to "opt_const -fine"	Clifford Wolf	2014-07-21
*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21
*	Added opt_const support for simple identities	Clifford Wolf	2014-07-21
*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18
*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17
*	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16
*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12
*	Fixed performance problem in opt_mux with nets driven by many conflicting dri...	Clifford Wolf	2014-03-19
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16
*	Fixed opt_const handling of double invert with non-1 output width	Clifford Wolf	2014-02-15
*	Added opt -purge (frontend to opt_clean -purge)	Clifford Wolf	2014-02-08