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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Improved TopoSort determinismClifford Wolf2014-11-07
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-31
* Fixed various VS warningsClifford Wolf2014-10-18
* Don't be too smart with $dff cells with "init" attribute on out signalClifford Wolf2014-10-16
* Some cleanups in opt_cleanClifford Wolf2014-10-16
* Wrapped init in std::set constructorWilliam Speirs2014-10-15
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-11
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* sat encoding for exclusive $pmux ctrl inputs in "share" passClifford Wolf2014-10-03
* added resource sharing of $macc cellsClifford Wolf2014-10-03
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* remove buffers in opt_cleanClifford Wolf2014-10-03
* resource sharing of $alu cellsClifford Wolf2014-10-03
* Added support for "keep" on modulesClifford Wolf2014-09-29
* namespace YosysClifford Wolf2014-09-27
* Re-enabled assert for new logic loops in "share" passClifford Wolf2014-09-21
* Various improvements regarding logic loops in "share" resultsClifford Wolf2014-09-21
* Logic loop bugfix for "share" passClifford Wolf2014-09-21
* Added "share -limit"Clifford Wolf2014-09-21
* Still loop bug in "share": changed assert to warningClifford Wolf2014-09-21
* Do not introduce new logic loops in "share"Clifford Wolf2014-09-21
* Assert on new logic loops in "share" passClifford Wolf2014-09-21
* Fixed wreduce $shiftx handlingClifford Wolf2014-09-15
* Cleanup in wreduceClifford Wolf2014-09-14
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added design->scratchpadClifford Wolf2014-08-30
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added "opt -fast"Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27