summaryrefslogtreecommitdiff
path: root/passes/opt
Commit message (Expand)AuthorAge
* Fixed wreduce $shiftx handlingClifford Wolf2014-09-15
* Cleanup in wreduceClifford Wolf2014-09-14
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added design->scratchpadClifford Wolf2014-08-30
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added "opt -fast"Clifford Wolf2014-08-16
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Added cover() calls to opt_constClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added "opt_const -keepdc"Clifford Wolf2014-07-21
* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-21
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
* Added opt_const support for simple identitiesClifford Wolf2014-07-21