yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed various VS warnings	Clifford Wolf	2014-10-18
*	Don't be too smart with $dff cells with "init" attribute on out signal	Clifford Wolf	2014-10-16
*	Some cleanups in opt_clean	Clifford Wolf	2014-10-16
*	Wrapped init in std::set constructor	William Speirs	2014-10-15
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	sat encoding for exclusive $pmux ctrl inputs in "share" pass	Clifford Wolf	2014-10-03
*	added resource sharing of $macc cells	Clifford Wolf	2014-10-03
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
*	remove buffers in opt_clean	Clifford Wolf	2014-10-03
*	resource sharing of $alu cells	Clifford Wolf	2014-10-03
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Re-enabled assert for new logic loops in "share" pass	Clifford Wolf	2014-09-21
*	Various improvements regarding logic loops in "share" results	Clifford Wolf	2014-09-21
*	Logic loop bugfix for "share" pass	Clifford Wolf	2014-09-21
*	Added "share -limit"	Clifford Wolf	2014-09-21
*	Still loop bug in "share": changed assert to warning	Clifford Wolf	2014-09-21
*	Do not introduce new logic loops in "share"	Clifford Wolf	2014-09-21
*	Assert on new logic loops in "share" pass	Clifford Wolf	2014-09-21
*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15
*	Cleanup in wreduce	Clifford Wolf	2014-09-14
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
*	Added "opt -fast"	Clifford Wolf	2014-08-16
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26