yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19
*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25
*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01
*	initial import	Clifford Wolf	2013-01-05