Commit message (Collapse) | Author | Age | |
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* | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 |
| | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||
* | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 |
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* | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 |
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* | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 |
| | | | | created interim RTLIL::SigSpec::chunks_rw() | ||
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
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* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
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* | Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst | Clifford Wolf | 2014-02-21 |
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* | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 |
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* | Added "proc_arst -global_arst" feature | Clifford Wolf | 2013-11-20 |
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* | Added handling of multiple async paths in proc_arst | Clifford Wolf | 2013-10-19 |
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* | Added nosync attribute and some async reset related fixes | Clifford Wolf | 2013-03-25 |
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* | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 |
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* | initial import | Clifford Wolf | 2013-01-05 |